Search - cpu vhdl

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[Windows Develop] CONTROL_UNIT DL : 0: control unit for multicycle cpu
Date : 2025-07-13 Size : 1kb User : a
[VHDL-FPGA-Verilog] cpu(FinalWithYS) DL : 0: verilog实现的八位CPU，包括乘法、除法以及多种寻址方式。代码中包括测试模块，可以直接在试验箱上运行。-verilog to achieve the eight CPU, including multiplication, division, as well as addressing a variety of ways. Code, including test modules, can be run directly in the chamber.
Date : 2025-07-13 Size : 8kb User : 鲁迪
[Other] cpu DL : 0: Date : 2025-07-13 Size : 1.58mb User : recome
[VHDL-FPGA-Verilog] Simple8bitCPU DL : 0: VHDL Source Code for Simple 8-bit CPU
Date : 2025-07-13 Size : 29kb User : MI
[VHDL-FPGA-Verilog] CPU DL : 0: Date : 2025-07-13 Size : 1.42mb User : 王霄洲
[VHDL-FPGA-Verilog] cpu_lynn DL : 0: Verilog 实现的简单单线程 CPU，基于计算机组成书目，思路清晰，有测试平台。-Verilog realization of a simple single-threaded CPU, the composition of computer-based bibliography, clear lines of thought, a test platform.
Date : 2025-07-13 Size : 11kb User : wei
[VHDL-FPGA-Verilog] cpu16 DL : 0: Verilog下描述16位CPU，虽然有点简单，但具有一定的可读性，内附夏宇闻老师的8位CPU文档-Verilog description of 16-bit CPU, though a bit simple, but with a certain degree of readability, XIA Yu-Wen teachers containing 8-bit CPU Documentation
Date : 2025-07-13 Size : 226kb User : 张文龙
[VHDL-FPGA-Verilog] DDCA_HDL_Examples DL : 0: mpis-CPU的VHDL语言设计，也包含了很多课件和例子。-MPIS-CPU
Date : 2025-07-13 Size : 46kb User : xiao ma
[VHDL-FPGA-Verilog] micro DL : 0: 16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
Date : 2025-07-13 Size : 30kb User : mojo
[SCM] CPU DL : 0: Simple 8 bit ALU which subs, adds, ands, ors, nots, ...
Date : 2025-07-13 Size : 3kb User : Emrah
[VHDL-FPGA-Verilog] cpusimple DL : 0: a simple vhdl of cpu
Date : 2025-07-13 Size : 6kb User : hafizm
[VHDL-FPGA-Verilog] cpu DL : 0: nios处理器代码，基于VHDL语言，很难道-nios processor code，vhdl code
Date : 2025-07-13 Size : 41kb User : 丁丁
[VHDL-FPGA-Verilog] cpu25 DL : 0: 8 bit cpu code using vhdl it performs various operations
Date : 2025-07-13 Size : 279kb User : anshu
[VHDL-FPGA-Verilog] 8bit_RISC_CPU_RTL_Code DL : 0: 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)
Date : 2025-07-13 Size : 78kb User : 曾亮
[VHDL-FPGA-Verilog] bc6502 DL : 0: VHDL实现的一个完整版的6502CPU硬件描述代码，包含了6502CPu的所有功能，附带VGA驱动以及输入输出控制-VHDL implementation of a full version of 6502CPU hardware description code, and includes all the features of 6502CPu, incidental VGA driver, as well as input and output control
Date : 2025-07-13 Size : 36kb User : Beijing
[VHDL-FPGA-Verilog] cpu_16bit DL : 0: design cpu 16 bits by verilog HDL.
Date : 2025-07-13 Size : 1kb User : tommy
[VHDL-FPGA-Verilog] 8bitRISCCPU DL : 0: 8bit RISC cpu 设计资料包含夏宇闻老师的教程第8章-8bit RISC cpu design
Date : 2025-07-13 Size : 797kb User : dyfdown
[Windows Develop] mipscpu-source DL : 0: mips cpu的实现.MIPS是世界上很流行的一种RISC处理器。MIPS公司的R系列就是在此基础上开发的RISC工业产品的微处理器。这些系列产品为很多计算机公司采用构成各种工作站和计算机系统。 -mips cpu implementation. MIPS is the world' s very popular as a RISC processor. MIPS company' s R series is based on the development of industrial products RISC microprocessor. These series of products for many computer companies used to create various workstations and computer systems.
Date : 2025-07-13 Size : 6.7mb User : 汤龑鸣
[VHDL-FPGA-Verilog] plan DL : 0: using the VHDL, 8bit cpu plan
Date : 2025-07-13 Size : 165kb User : Kim
[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24 DL : 0: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Date : 2025-07-13 Size : 4.72mb User : 石

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